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19-1507; Rev 0a; 8/99
ANUAL N KIT M LUATIO ATA SHEET EVA WS D FOLLO
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
Features
o Complete IF Subsystem Includes VCO and Synthesizer o Supports Dual-Band, Triple-Mode Operation o VGA with >110dB Gain Control o Quadrature Demodulator o High Output Level (2.7V) o Programmable Charge-Pump Current o Supports Any IF Frequency Between 40MHz and 300MHz o 3-Wire Programmable Interface o Low Supply Voltage (+2.7V)
General Description
The MAX2310/MAX2312/MAX2314/MAX2316 are IF receivers designed for dual-band, dual-mode, and single-mode N-CDMA and W-CDMA cellular phone systems. The signal path consists of a variable gain amplifier (VGA) and I/Q demodulator. The devices feature guaranteed +2.7V operation, a dynamic range of over 110dB, and high input IP3 (-33dBm at 35dB gain, 1.7dBm at -35dB). Unlike similar devices, the MAX2310 family of receivers includes dual oscillators and synthesizers to form a self-contained IF subsystem. The synthesizer's reference and RF dividers are fully programmable through a 3-wire serial bus, enabling dual-band system architectures using any common reference and IF frequency. The differential baseband outputs have enough bandwidth to suit both N-CDMA and W-CDMA systems, and offer saturated output levels of 2.7Vp-p at a low +2.75V supply voltage. Including the low-noise voltage-controlled oscillator (VCO) and synthesizer, the MAX2310 draws only 26mA from a +2.75V supply in CDMA (differential IF) mode. The MAX2310/MAX2312/MAX2314/MAX2316 are available in 28-pin QSOP packages.
MAX2310/MAX2312/MAX2314/MAX2316
Ordering Information
PART MAX2310EEI MAX2312EEI MAX2314EEI MAX2316EEI TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 28 QSOP 28 QSOP 28 QSOP 28 QSOP
Applications
Single/Dual/Triple-Mode CDMA Handsets Globalstar Dual-Mode Handsets Wireless Data Links Tetra Direct-Conversion Receivers Wireless Local Loop (WLL)
Pin Configurations appear at end of data sheet. Block Diagram appears at end of data sheet.
Selector Guide
PART MAX2310 MAX2312 MAX2314 MODE AMPS, Cellular CDMA, PCS CDMA PCS CDMA AMPS, Cellular CDMA Cellular CDMA DESCRIPTION Dual Band, Triple Mode Single Band, Single Mode Single Band, Dual Mode Single Band, Single Mode or Single Band, Dual Mode with External Discriminator INPUT RANGE 40MHz to 300MHz 67MHz to 300MHz 40MHz to 150MHz
MAX2316
40MHz to 150MHz
________________________________________________________________ Maxim Integrated Products
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.3V, +6.0V SHDN to GND.............................................-0.3V to (VCC + 0.3V) STBY, BUFEN, MODE, EN, DATA, CLK, DIVSEL ...........................................-0.3V to (VCC + 0.3V) VGC to GND...............-0.3V, the lesser of +4.2V or (VCC + 0.3V) AC Signals TankH , TankL , REF, FM , CDMA .................................................1.0V peak Digital Input Current SHDN, MODE, DIVSEL, BUFEN, DATA, CLK, EN, STBY .....................................10mA Continuous Power Dissipation (TA = +70C) 28-pin QSOP (derate 10mW/C above TA = +70C) ....800mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, MODE = DIVSEL = SHDN = STBY = BUFEN = high, differential output load = 10k, TA = -40C to +85C, registers set to default power-up settings. Typical values are at VCC = +2.75V and TA = +25C, unless otherwise noted.) PARAMETER SYMBOL CDMA mode FM IQ mode FM I mode STANDBY (VCO_H) STANDBY (VCO_L) CONDITIONS TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C 3.5 1.5 3 2.0 0.5 IIH IIL 0.5V < VVGC < 2.3V SHDN = low 50k load 50k load I+ to I- and Q+ to Q-, PLL locked VCC = 2.75V -20 1.5 VCC - 1.4 2.0 0.5 +20 -5 2 2 5 1 10 5.8 A mA V V A A A A V V mV V 11.5 12.3 24.7 25.4 MIN TYP 25.9 MAX 37.5 41.5 36.7 40.6 35.7 39.5 18.8 20.7 18.4 20.3 mA UNITS
Supply Current (Note 1)
ICC ICC
Addition for LO out (BUFEN = low) Shutdown Current Register Shutdown Current Logic High Logic Low Logic High Input Current Logic Low Input Current VGC Control Input Current VGC Control Input Current During Shutdown Lock Indicator High (locked) Lock Indicator Low (unlocked) DC Offset Voltage Common-Mode Output Voltage ICC ICC SHDN = low
2
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
AC ELECTRICAL CHARACTERISTICS
(MAX2310/MAX2314 or MAX2312/MAX2316 EV kit, VCC = +2.75V, registers set to default power-up states, fIN = 210.88MHz for CDMA, fIN = 85.88MHz for FM, fREF = 19.68MHz, synthesizer locked with passive 2nd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10k, all power levels referred to 50, TA = +25C, unless otherwise noted.) PARAMETER Input Frequency Reference Frequency Frequency Reference Signal Level SIGNAL PATH, CDMA MODE Input Third-Order Intercept Input 1dB Compression Input 0.25dB Desensitization Minimum Voltage Gain Maximum Voltage Gain DSB Noise Figure SIGNAL PATH, FM_IQ MODE Input Third-Order Intercept Input 1dB Compression Minimum Voltage Gain Maximum Voltage Gain Maximum Gain Variation Over Temperature Baseband 0.5dB Bandwidth Quadrature Suppression LO to Baseband Leakage Saturated Output Level PHASE-LOCKED LOOP VCO Tune Range LOOUT Output Power fVCO_L fVCO_H PLO (Note 2) RL = 50, BUFEN = low 80 135 -13.7 300 600 MHz dBm VSAT Differential TA = TMIN to TMAX +30 IIP3 P1dB AV AV (Note 7) (Notes 6, 8) VGC = 0.5V (Note 6) VGC = 2.3V (Note 6) 58.5 Gain = -35dB Gain = +35dB Gain = -35dB Gain = +35dB -20 -44 -6.0 -31 -16.2 -38.4 -50.2 63.4 -47.4 dBm dBm dB dB AV AV NF IIP3 P1dB Gain = -35dB (Note 3) Gain = +35dB (Note 4) Gain = -35dB Gain = +35dB (Note 5) VGC = 0.5V (Note 6) VGC = 2.3V (Note 6) Gain = -35dB Gain = +35dB 56 Gain = -35dB Gain = +35dB -9 -44 1.7 -33.2 -6.4 -38.3 -14.8 -49 -54.8 61.3 62.9 6.36 -49 dBm dBm dBm dB dB dB SYMBOL fIN fREF VREF (Note 2) (Note 2) 0.2 CONDITIONS MIN 40 TYP MAX 300 39 UNITS MHz MHz Vp-p
MAX2310/MAX2312/MAX2314/MAX2316
SIGNAL PATH, CDMA and FM_IQ MODE Normalized to +25C 2.5 4.2 +35 1 2.7 dB MHz dB mVp-p Vp-p
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2310/MAX2314 or MAX2312/MAX2316 EV kit, VCC = +2.75V, registers set to default power-up states, fIN = 210.88MHz for CDMA, fIN = 85.88MHz for FM, fREF = 19.68MHz, synthesizer locked with passive 2nd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10k, all power levels referred to 50, TA = +25C, unless otherwise noted.) PARAMETER VCO Minimum Divide Ratio VCO Maximum Divide Ratio REF Minimum Divide Ratio REF Maximum Divide Ratio Minimum Phase Detector Comparison Frequency Maximum Phase Detector Comparison Frequency Base Band Spurious due to PLL 1kHz offset 12.5kHz offset LOOUT at 85MHz, VCO_L Enabled (Note 9) 30kHz offset 120kHz offset 900kHz offset 1kHz offset 12.5kHz offset LOOUT at 210MHz, VCO_H Enabled (Note 9) 30kHz offset 120kHz offset 900kHz offset TURBO LOCK Acquisition, CPX = XX, TC = 1 Locked, CPX = 00 Charge-Pump Source/Sink Current Locked, CPX = 01 Locked, CPX = 10 Locked, CPX = 11 Charge-Pump Source/Sink Matching Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Locked, all values of CPX, 0.5V < VCP < VCC - 0.5V 1480 105 150 210 300 2100 150 210 300 425 0.2 2650 190 265 380 530 10 % A -72 -100 -110 -119 -125 -64 -91 -105 -115 -125 dBc/Hz dBc/Hz SYMBOL M1, M2 M1, M2 R1, R2 R1, R2 (Note 6) (Note 6) 1500 -50 2047 20 kHz kHz dBc 16383 2 CONDITIONS MIN TYP MAX 256 UNITS
FM_IQ and FM_I modes are not available on MAX2312 and MAX2316. Recommended operating frequency range. f1 = 210.88MHz, f2 = 210.89MHz, Pf1 = Pf2 = -15dBm. f1 = 210.88MHz, f2 = 210.89MHz, Pf1 = Pf2 = -50dBm. Small-signal gain at 200kHz below the LO frequency will be reduced by less than 0.25dB when an interfering signal at 1.25MHz below the LO frequency is applied at the specified level. Guaranteed by design and characterization. f1 = 85.88MHz, f2 = 85.98MHz, Pf1 = Pf2 = -15dBm. f1 = 85.88MHz, f2 = 85.98MHz, Pf1 = Pf2 = -50dBm. Measured at LOOUT with BD = 0 (/2 selected).
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
Typical Operating Characteristics
(MAX2310/MAX2314 or MAX2312/MAX2316 EV kit, VCC = +2.75V, registers set to default power-up states, fIN = 210.88MHz for CDMA, fIN = 85.88MHz for FM, fREF = 19.68MHz, synthesizer locked with passive 2nd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10k, all power levels referred to 50, TA = +25C, unless otherwise noted.)
RECEIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX2310 toc01
MAX2310/MAX2312/MAX2314/MAX2316
RECEIVE SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
MAX2310 toc02
GAIN vs. VGC
60 40 GAIN (dB) 20 0 -20 -40 TA = +25C TA = -40C TA = +85C
NAX2310 toc03
35.00 32.50 SUPPLY CURRENT (mA) TA = +85C 30.00 27.50 25.00 22.50 20.00 2.5 3.0 3.5 4.0 4.5 5.0 TA = +25C
0.014 0.012 SHUTDOWN CURRENT (mA) 0.010 0.008 TA = +25C 0.006 0.004 0.002 0 TA = -40C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TA = +85C
80
TA = -40C
-60 -80 5.5 0.5 1.0 1.5 2.0 2.5 3.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
VGC (V)
GAIN vs. INPUT FREQUENCY
MAX2310 toc04
GAIN vs. BASEBAND FREQUENCY
MAX2310 toc05
THIRD-ORDER INPUT INTERCEPT vs. GAIN
TA = -40C
MAX2310 toc06
60 55 50 45 GAIN (dB) 40 35 30 25 20 15 0 100 200 300 400 VGC = 2.5V
60.0 59.5 RELATIVE GAIN (dB) 59.0
10 0 -10 IIP3 (dBm)
58.5 58.0 57.5
TA = +85C -20 -30 -40 TA = +25C
57.0 56.5 500 56.0 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) -50 -60 -60 -40 -20 0 20 40 60 80 GAIN (dB)
FREQUENCY (MHz)
NOISE FIGURE vs. GAIN
MAX2310 toc07
NOISE FIGURE vs. TEMPERATURE
MAX2310 toc08
VCO VOLTAGE vs. TIME
MAX2310 toc09
70 60 50 NF (dB) 40 30 20 10
7.4 7.2 7.0 NF (dB) 6.8 6.6 6.4 6.2 6.0 -40 -20 0 20 40 60 80
SHDN VCO VOLTAGE VOLTS (1V/div)
LOCK
LOCK TIME 1.83ms
0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 GAIN (dB)
100
TIME (500s/div)
TEMPERATURE (C)
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
Typical Operating Characteristics (continued)
(MAX2310/MAX2314 or MAX2312/MAX2316 EV kit, VCC = +2.75V, registers set to default power-up states, fIN = 210.88MHz for CDMA, fIN = 85.88MHz for FM, fREF = 19.68MHz, synthesizer locked with passive 2nd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10k, all power levels referred to 50, TA = +25C, unless otherwise noted.)
FM PORT S11 vs. FREQUENCY
MAX2310 toc10
TANKL PORT 1/S11 vs. FREQUENCY
MAX2310 toc11
TANKH PORT 1/S11 vs. FREQUENCY
MAX2310 toc12
4 3 2 1
4 3 2 1
1
2 4 3 1: 2: 3: 4: 641 - j428 10MHz 27 - j162 85MHz 4 - j73 210MHz 1.8 - j39 600MHz 1: 2: 3: 4: -3.06ms + j349s, 100MHz -3.01ms + j853s, 160MHz -3.11ms + j1.45ms, 240MHz -3.04ms + j1.85ms, 300MHz 1: 2: 3: 4: 1.98ms + j437s, 100MHz 2.18ms + j853s, 160MHz 2.11ms +j 2.53ms, 420MHz 2.17ms +j 3.71ms, 600MHz
LOOUT PORT S22 vs. FREQUENCY
MAX2310 toc13
CDMA PORT S11 vs. FREQUENCY
MAX2310 toc14
1: 108.63 (Re) 10.266 (1m) 40MHz 2: 134.99 (Re) 13.71 (1m) 150MHz 3: 158.83 (Re) 39.58 (1m) 300MHz
1 2 3 4 1: 10MHz, 375 - j56 2: 85MHz, 285 - j200 3: 210MHz, 73 - j169 4: 600MHz, 2.1 - j34
Pin Description
PIN MAX2310 1 2 3 4, 5 -- MAX2312 1 2 3 -- 4 MAX2314 1, 8 2 3 4, 5 -- MAX2316 1 2 3 5, 6 4 NAME BYP CP_OUT GND TANKL+, TANKLDIVSEL FUNCTION Bypass Node. Must be capacitively decoupled (bypassed) to analog ground. Charge-Pump Output Analog Ground Reference Differential Tank Input for Low-Frequency Oscillator High selects M1/R1; low selects M2/R2.
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
Pin Description (continued)
PIN MAX2310 6, 7 -- -- 8 MAX2312 5, 6 7 -- -- MAX2314 -- -- 6, 7 -- MAX2316 -- 7 -- -- NAME TANKH+, TANKHBUFEN N.C. MODE FUNCTION Differential Tank Input for High-Frequency Oscillator LO Buffer Amplifier--active low No Connection. Must be left open-circuit. Mode Select. High selects CDMA mode; low selects FM mode. Internal VCO Output. Depending on setting of BD bit, LOOUT is either the VCO frequency (twice the IF frequency) or onehalf the VCO frequency (equal to the IF frequency). +2.7V to +5.5V Supply for Digital Circuits Digital Ground Reference Frequency Input Shutdown Input--active low. Low powers down entire device, including registers and serial interface. Differential In-Phase Baseband Output, or FM signal output FM_I mode is selected. Lock Output--open-collector pin. Logic high indicates phaselocked condition. Differential Quadrature-Phase Baseband Output. Disabled if FM_I mode is selected. Clock input of the 3-wire serial bus Enable Input. When low, input shift register is enabled. Data input of the 3-wire serial bus. 2.7V to 5.5V Supply for Analog Circuits VGA Gain Control Input. Control voltage range is 0.5V to 2.3V. Differential CDMA Input. Active in CDMA mode. Differential Positive Input. Active in FM mode. No Connection. Differential Negative Input for FM signal. Bypass to GND for single-ended operation. Standby Input--active low. Low powers down VGA and demodulator while keeping VCO, PLL, and serial bus on. Bypass Node. Must be capacitively decoupled (bypassed) to analog VCC.
MAX2310/MAX2312/MAX2314/MAX2316
-- 9 10 11 12 13, 14 15 16, 17 18 19 20 21 22 23, 24 25 -- 26 -- 27, 28
8 9 10 11 12 13, 14 15 16, 17 18 19 20 21 22 23, 24 -- 25 -- 26 27, 28
-- 9 10 11 12 13, 14 15 16, 17 18 19 20 21 22 23, 24 25 -- 26 -- 27, 28
8 9 10 11 12 13, 14 15 16, 17 18 19 20 21 22 23, 24 -- 25 -- 26 27, 28
LOOUT VCC GND REF SHDN IOUT+, IOUTLOCK QOUT-, QOUT+ CLK EN DATA VCC VGC CDMA-, CDMA+ FM+ N.C. FMSTBY BYP
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
47pF 10k 0.01F 0.033F 3.3nF BYP CPOUT GND 10k 18pF TANKL+ 5pF 10k 18pF 68nH BYP BYP FMFM+ CDMA+ FM 0.01F 0.1F 0.01F VCC
MAX2310
TANKLCDMATANKH+ VGC
680
CDMA
10k
12pF
DAC 47pF
1.5pF 10k 12pF
18nH TANKHMODE
VCC
VCC DATA EN 3-WIRE
VCC 47pF
VCC GND REF SHDN IOUT+
CLK
QOUT+ 10k Q
I
10k IOUTQOUTLOCK
47k
VCC
Figure 1. MAX2310 Typical Operating Circuit
_______________Detailed Description
MAX2310
The MAX2310 is intended for dual-band (PCS and cellular) and dual-mode code division multiple access (CDMA) and FM applications (Figure 1). The device includes an IF variable-gain amplifier, quadrature demodulator, dual VCOs, and dual-frequency synthesizers (Figure 7). Dual VCOs are provided for applications using different IF frequencies for each mode or band of operation. The analog FM output signal can be
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configured for conversion to the I channel, or it may be converted in quadrature to both the I and Q channels. The MAX2310's operation modes are described in Table 1. These modes are set by programming the control register and setting logic levels on control pins. If MODE is left floating, the internal register controls the operation. If driven high or low, mode will override certain register bits, as shown in Table 1.
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
Table 1. MAX2310 Control Register States
PINS M S B M CONTROL REGISTER S B L S B
MAX2310/MAX2312/MAX2314/MAX2316
TEST_MODE
VCO_BYP
VCO_SEL
FM_TYPE
TEST_EN
BUF_DIV
CP POL
DIVSEL
IN_SEL
BUFEN
MODE
SHDN
SHUTDOWN SHUTDOWN STANDBY CDMA CDMA FM_IQ FM_IQ FM_I FM_I
Shutdown pin completely powers down the chip 0 in shutdown register bit leaves serial port active 0 in standby register bit turns off VGA and modulator only Mode pin overrides VCO_SEL, DIVSEL, and IN_SEL to high Floating mode pin returns control to register Mode pin overrides VCO_SEL, DIVSEL, and IN_SEL to low Floating mode pin returns control to register Mode pin overrides VCO_SEL, DIVSEL, and IN_SEL to low Floating pins return control to register
L H H H H H H H H L
X X X H F L F L F
X X X
X X X
X X 0 0 0 0 0 0 0
X X
X X
X X
X X
X X X
X X X X X X X X X
X X
X X
X X 0
X 1 X
X 1 X
X X X X
X X 0 0 1 1
X 1 X 0 X 0
1 1 1 1 1 1
X
X
X X
Note: H = high, L = low, F = floating pin, X = don't care, Blank = independent parameter, 1 = logic high, 0 = logic low.
MAX2312/MAX2316
The MAX2312/MAX2316 quadrature demodulators are simplified versions of the MAX2310 that can be used in single-mode CDMA or dual mode using an external FM discriminator (Figures 2a and 2b). The MAX2312 VCO is optimized for the 67MHz to 300MHz IF frequency range, while the MAX2316 VCO is optimized for the 40MHz to 150MHz IF frequency range. Both devices include a buffered output for the VCO. The buffered VCO output can be used to support systems implementing traditional limiting IF stages for FM demodulation in dual-mode phones as well as for the transmit LO in TDD systems. This buffered output can
be configured for the VCO frequency (twice the IF frequency) or one-half the VCO frequency (IF frequency). The BUFEN pin enables this feature. A standby mode, in which only the VCO and synthesizer are operational, can be selected through the serial interface or the STBY pin. The MAX2312/MAX2316s' operational modes are described in Table 2. These modes are set by programming the control register and/or setting logic levels on control pins. If the control pins (STBY, BUFEN, DIVSEL) are left floating, the internal register controls the operational mode. If driven high or low, the control pins will override certain register bits, as shown in Table 2.
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SHDN X 0 1 1 1 1 1 1 1 9
STBY
OPERATIONAL MODE
ACTION RESULT
TURBOCHARGE
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
47pF 10k 0.01F 0.033F 3300pF BYP BYP 0.01F CPOUT GND 10k 12pF DIVSEL TANKH+ 1.5pF 10k 12pF 18nH CDMA+ 680 CDMA BYP STBY VCC 0.01F VCC
MAX2312
TANKHBUFEN LOOUT CDMAVGC 47pF VCC DATA EN CLK QOUT+ 10k IOUTQOUTLOCK 47k Q 3-WIRE DAC
VCC 47pF
VCC GND REF SHDN IOUT+ VCC
I
10k
VCC
Figure 2a. MAX2312 Typical Operating Circuit
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
47pF 0.033F 0.01F 10k 3300pF CP_OUT GND 10k 17pF DIVSEL TANKL+ 5pF 10k 18pF 68nH CDMA+ 680 CDMA BYP STBY BYP BYP 0.01F VCC 0.01F VCC
MAX2316
TANKLCDMAVGC 47pF LOOUT VCC DATA EN CLK QOUT+ 10k IOUTQOUTLOCK 47k Q 3-WIRE VCC DAC
DISCRIMINATOR
BUFEN
455kHz
VCC 47pF
VCC GND REF SHDN IOUT+
LIMITER
I
10k
FM
VCC
Figure 2b. MAX2316 Typical Operating Circuit
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
Table 2. MAX2312/MAX2316 Control Register States
PINS M S B CONTROL REGISTER MSB L S B
TEST_MODE
VCO_BYP
VCO_SEL
FM_TYPE
TES_TEN
BUF_DIV
CP_POL
DIVSEL
DIVSEL
IN_SEL
BUFEN
BUFEN
SHDN
SHUTDOWN
Shutdown pin completely powers down the chip 0 in shutdown register bit leaves serial bus active 0 in standby pin turns off VGA and modulator only 0 in standby register bit turns off VGA and modulator only DIV_SEL pin overrides DIV_SEL register bit If DIV_SEL pin is floated, then register bit selects divider BUFEN pin controls the LO buffer and overrides the bit If pin is floated, then BUFEN register bit controls buffer
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SHUTDOWN
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
STANDBY
H
L
0
X
X
STANDBY DIVIDER SELECT DIVIDER SELECT LO BUFFER ENABLE LO BUFFER ENABLE
H
H/ L H/ L F
H
0
X
0
H
H
0
X 1/ 0
X
H
H
0
X
H/ L
H
0
X
X
H
F
0
X
1/ 0
Note: H = high, L = low, 1 = logic high, 0 = logic low, X = don't care, blank = independent parameter.
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SHDN X 0 1 1 1 1 1 1
STBY
STBY
OPERATIONAL MODE
ACTION RESULT
TURBOCHARGE
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
47pF
10k 0.01F BYP 0.033F 3300pF BYP 0.01F VCC 0.01F BYP 0.01F FMTANKL+ FM+ 5pF 10k 18pF TANKL1000pF BYP CDMAVGC VCC 47pF GND REF SHDN I_OUT+ 10k I_OUTQ_OUTLOCK 47k DATA EN CLK Q_OUT+ 10k Q 3-WIRE VCC VCC VCC 47pF DAC 680 CDMA 68nH CDMA+ FM VCC
MAX2314
CP_OUT 10k 18pF GND
VCC
Figure 3. MAX2314 Typical Operating Circuit
MAX2314
The MAX2314 supports CDMA cellular-band, dualmode operation. As with the MAX2310, the FM mode can be configured for conversion to the I port or quadrature conversion to both the I and Q ports (Figure 3). The MAX2314's operational modes are described in Table 3. These modes are set by programming the control register and setting logic levels on control pins.
__________Applications Information
Variable-Gain Amplifier and Demodulator
The MAX2310 family provides a Variable-Gain Amplifier (VGA) with exceptional gain range. The MAX2310/ MAX2314 support multimode applications with dual differential inputs, selectable with the IN_SEL (IS) control bit. On the MAX2310 this function can be controlled with the MODE pin, which overrides the IS control bit. The VGA's gain is controlled over a 110dB range with
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
Table 3. MAX2314 Control Register States
P I N M S B M CONTROL REGISTER S B L S B
TEST_MODE
VCO_BYP
VCO_SEL
FM_TYPE
TEST_EN
BUF_DIV
CP_POL
DIVSEL
IN_SEL
BUFEN
SHDN
SHUTDOWN SHUTDOWN STANDBY CDMA FM_IQ FM_I
Shutdown pin completely shuts down chip 0 in shutdown register bit leaves serial port active 0 in standby pin turns off VGA and modulator only CDMA operation FM IQ quadrature operation FM I operation
L H H H H H
X X
X X
X X 0 0 0 0
X X
X X
X X
X X 0 0 0 0
X X X X X X
X X X X X X
X X
X X
X X 0
X 0 1
1 0 0
1 1 1
Note: H = high, L = low, 1 = logic high, 0 = logic low, X = don't care, blank = independent parameter
the VGC pin. The output of the VGA drives the RF ports of a quadrature demodulator. The MAX2310/MAX2314 provide two types of FM demodulation, controlled by the FM_TYPE (FT) control bit. When FM_TYPE is "1," the signal is passed through both the I and Q signal paths for subsequent lowpass filtering and A/D conversion at baseband. If FM_TYPE is "0," the FM signal is passed through the I mixer only.
Voltage-Controlled Oscillator, Buffers, and Quadrature Generation
The LO signal for downconversion is provided by a voltage-controlled oscillator (VCO) consisting of an onchip differential oscillator, and an off-chip high-Q resonant network. Figure 4 shows a simplified schematic of the VCO oscillator. Multiband operation is supported by the MAX2310 with dual VCOs. VCO_H and VCO_L are selectable with the MODE pin or the VCO_SEL (VS)
control bit. They oscillate at twice the desired LO frequency. For applications requiring an external LO, the VCOs can be bypassed with the VCO_BYP (VB) control bit. The MAX2312/MAX2316 buffer the output of the VCO and provide this signal at the LOOUT pin. This signal is enabled by the BUFEN (BE) control bit or by the BUFEN control pin. The frequency of this signal is selected by the BUF_DIV (BD) control bit, and can be either the VCO frequency or half the VCO frequency. Quadrature downconversion is realized by providing inphase (I) and quadrature-phase (Q) components of the LO signal to the LO ports of the demodulator described above. The quadrature LO signals are generated by dividing the VCO output frequency using two latches. The appropriate latch outputs provide I and Q signals at the desired LO frequency.
14
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SHDN X L 1 1 1 1
STBY
OPERATIONAL MODE
ACTION RESULT
TURBOCHARGE
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
Synthesizer
The VCO's output frequency is controlled by an internal phase-locked-loop (PLL) dual-modulus synthesizer. The loop filter is off-chip to simplify loop design for emerging applications. The tunable resonant network is also off-chip for maximum Q and for system design flexibility. The VCO output frequency is divided down to the desired comparison frequency with the M counter. The M counter consists of a 4-bit A swallow counter and a 10-bit P counter. A reference signal is provided from an external source and is divided down to the comparison frequency with the R counter. The two divided signals are compared with a three-state digital phase-frequency detector. The phase-detector output drives a charge pump as well as lock-detect logic and turbocharge control logic. The charge pump output (CP_OUT) pin is processed by the loop filter and drives the tunable resonant network, altering the VCO frequency and closing the loop. Multimode applications are supported by two independent programmable registers each for the M counter (M1, M2), the R counter (R1, R2), and the charge-pump output current magnitude (CP1, CP2). The DIVSEL (DS) bit selects which set of registers is used. It can be overridden by the MAX2310's MODE pin or the MAX2312/ MAX2316's DIVSEL pin. Programming these registers is discussed in the 3-Wire Interface and Registers section. When the part initially powers up or changes state, the synthesizer acquisition time can be reduced by using the Turbo feature, enabled by the TURBOCHARGE (TC) control bit. Turbo functionality provides a larger charge-pump current during acquisition mode. Once the VCO frequency is acquired, the charge-pump output current magnitude automatically returns to the preprogrammed state to maintain loop stability and minimize spurs in the VCO output signal. The lock detect output indicates when the PLL is locked with a logic high.
MAX2310/MAX2312/MAX2314/MAX2316
3-Wire Interface and Registers
The MAX2310 family incorporates a 3-wire interface for synthesizer programming and device configuration (Figure 5). The 3-wire interface consists of a clock, data, and ENABLE. It controls the VCO dividers (M1 and M2), reference frequency dividers (R1 and R2), and a 13-bit control register. The control register is used to set up the operational modes (Table 4). The input shift is 17 data bits long and requires a total of 18 clock bits (Figure 6). A single clock pulse is required before enable drops low to initialize the data bus. Whenever the M or R divide register value is programmed and downloaded, the control register must also be subsequently updated. This prevents turbolock from going active when not desired. The SHDN control bit is notable because it differs from the SHDN pin. When the SHDN control bit is low, the registers and serial interface are left active, retaining the values stored in the latches, while the rest of the device is shut off. In contrast, the SHDN pin, when low, shuts down everything, including the registers and serial interface. See the functional diagram in Figure 7.
800A
D1 R1 TANK+ RL CF RB RB CF RL TANK-
Registers
Figure 8 shows the programming logic. The 17-bit shift register is programmed by clocking in data at the rising edge of CLK. Before the shift register is able to accept data, it must be initialized by driving it with at least one full clock cycle at the CLK input with EN high (see Figure 6). Pulling enable low will allow data to be clocked into the shift register; pulling enable high loads the register addressed by A0, A1, and A2, respectively (Figure 8). Table 5 lists the power-on default values of all registers. Table 6 lists the charge-pump current, depending on CP0 and CP1.
RE
RE
Figure 4. Voltage-Controlled Oscillators
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
VCO1
14-BIT M1 COUNTER (00) DATA CLK EN START BIT M U X 16-BIT DATA/ADDRESS REGISTER (11X) 13-BIT CONTROL REGISTER CP2 (01) (010) (011) 2-BIT CP2 11-BIT R2 COUNTER 2-BIT CP1 11-BIT R1 COUNTER FREF CPOUT CPI
VCO2
14-BIT M2 COUNTER
Figure 5. 3-Wire Control Block Diagram
MSB DATA *SB *START BIT MUST BE LOGIC HIGH. * CLOCK *RISE AND FALL REQUIRED PRIOR TO EN GOING LOW. ENABLE
LSB
Figure 6. 3-Wire Interface Timing Diagram
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
MAX2310 MAX2312 MAX2314 MAX2316
VGC CDMA+ CDMASB 1 SHIFT REGISTER LOGIC EN CLK DATA (MAX2310/14) FM+ FMM1 REGISTER 00 14 FT /2 QOUT+ QOUTIOUT+ IOUT-
M2 REGISTER 2 010
01
14 DIVSEL (MAX2312/16)
CP1
R1 REGISTER
11
MODE (MAX2310) IS VS
2
CP2
R2 REGISTER
011
11
TM POL TE
TC
DS
VB
VS
BD BE
FT
IS
SB
SD 110
DS VCO_L 14 14 TANKL+
CONTROL 2 2 11 11
2
11 R COUNTER
14 M COUNTER VB
TANKL-
REF POL O DET LOCK DET TANKH+ TANKH-
TURBO CONTROL 2 CHARGE PUMP
TC
VCO_H
LOCK
SHDN
BIAS CP_OUT
/2
LO_OUT BUFEN
STBY (MAX2312/16)
BD SB SD
BE (MAX2312/16)
Figure 7. Functional Diagram
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
Table 4. Control Register, Default State: 0B57h, Address: 110b
BIT ID TM BIT NAME TEST_MODE POWERUP STATE 0 BIT LOCATION 0 = LSB 12 FUNCTION Must be 0 for normal operation. Logic "1" causes the charge-pump output CP_OUT to source current when fREF/R > fVCO/M. This state is used when the VCO tune polarity is such that increasing voltage produces increasing frequency. Logic "0" causes CP_OUT to source current when fVCO/M > fREF/R. This state is used when increasing tune voltage causes the VCO frequency to decrease. Must be 0 for normal operation. Logic "1" activates turbocharge mode, which provides rapid frequency acquisition in the PLL. Logic "1" selects M1/R1 divide ratios. Logic "0" selects M2/R2. Logic "1" bypasses the VCO inputs for external VCO operation. Logic "1" selects VCO_H. Logic "0" selects VCO_L. Logic "1" selects divide-by-2 on LOOUT port. Logic "0" bypasses divider. Logic "1" disables LOOUT. Logic "0" enables LOOUT. Active in FM mode. Logic "0" selects quadrature demodulator for FM mode. Logic "1" selects downconversion to I port. Logic "0" selects FM input port. Logic "1" selects CDMA input. Logic "0" enables standby mode, which shuts down the VGA and demodulator stages, leaving the VCO locked and the registers active. Logic "0" enables register-based shutdown. This mode shuts down everything except the M and R latches and the serial bus.
POL
CP_POL
1
11
TE TC DS VB VS BD BE FT IS SB
TEST_ENABLE TURBO_CHARGE DIV_SEL VCO_BYP VCO_SEL BUF_DIV BUFEN FM_TYPE IN_SEL STBY
0 1 1 0 1 0 1 0 1 1
10 9 8 7 6 5 4 3 2 1
SD
SHDN
1
0
Table 5. Register Defaults
REGISTER M1 M2 R1 R2 CTRL CP0 CP1 DEFAULT 10519DEC 4269DEC 492DEC 492DEC OB57HEX 11 BIN 11 BIN
Table 6. Charge-Pump Control Bits
CP1 0 0 1 1 CP0 0 1 0 1 CHARGE-PUMP CURRENT AFTER ACQUISITION (A) 150 210 300 425
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
ADDRESS DECODED START BIT SHIFT REGISTER 1 A2/M0 A2/M0 A1 A1 A0 A0 DATA
M1 REGISTER
M113
M1/0
0
0
M2 REGISTER
M213
M2/0
0
1
CP1 AND R1 REGISTERS
CP1/1 CP1/0 R1/10
R1/0
0
1
0
CP2 AND R2 REGISTERS
CP2/1 CP2/0 R2/10
/1
R2/0
0
1
1
CTRL REGISTER
TM
POL
TE
TC
DS
VB
VS
BD
BE
FT
IS
SB
SD
1
1
0
Figure 8. Programming Logic
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
Pin Configurations
TOP VIEW
BYP 1 CP_OUT 2 GND 3 TANKL+ 4 TANKL- 5 TANKH+ 6 TANKH- 7 MODE 8 VCC 9 GND 10 REF 11 SHDN 12 IOUT+ 13 IOUT- 14 28 BYP 27 BYP 26 FM25 FM+ 24 CDMA+ BYP 1 CP_OUT 2 GND 3 TANKL+ 4 TANKL- 5 N.C. 6 N.C. 7 BYP 8 VCC 9 GND 10 REF 11 SHDN 12 IOUT+ 13 IOUT- 14 28 BYP 27 BYP 26 FM25 FM+ 24 CDMA+
MAX2310
23 CDMA22 VGC 21 VCC 20 DATA 19 EN 18 CLK 17 QOUT+ 16 QOUT15 LOCK
MAX2314
23 CDMA22 VGC 21 VCC 20 DATA 19 EN 18 CLK 17 QOUT+ 16 QOUT15 LOCK
QSOP
QSOP
BYP 1 CPOUT 2 GND 3 DIVSEL 4 TANKH+ 5 TANKH- 6 BUFEN 7 LOOUT 8 VCC 9 GND 10 REF 11 SHDN 12 IOUT+ 13 IOUT- 14
28 BYP 27 BYP 26 STBY 25 N.C. 24 CDMA+
BYP 1 CP_OUT 2 GND 3 DIVSEL 4 TANKL+ 5 TANKL- 6 BUFEN 7 LOOUT 8 VCC 9 GND 10 REF 11 SHDN 12 IOUT+ 13 IOUT- 14
28 BYP 27 BYP 26 STBY 25 N.C. 24 CDMA+
MAX2312
23 CDMA22 VGC 21 VCC 20 DATA 19 EN 18 CLK 17 QOUT+ 16 QOUT15 LOCK
MAX2316
23 CDMA22 VGC 21 VCC 20 DATA 19 EN 18 CLK 17 QOUT+ 16 QOUT15 LOCK
QSOP
QSOP
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
Chip Information
TRANSISTOR COUNT: 6422
MAX2310/MAX2312/MAX2314/MAX2316
Block Diagram
DAC VCC
AVCC BYP BYP FMFM+ CDMA+ CDMAVGA DATA EN CLK
QOUT+ QOUT- LOCK VCC
0
90 /2
MAX2310
/M CHARGE PUMP PHASE DETECTOR /R BYP CP_OUT AGND TANKL+ TANKLTANKH+ TANKHREF MODE DVCC SHDN IOUT+ IOUT-
______________________________________________________________________________________
21
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2310/MAX2312/MAX2314/MAX2316
Package Information
QSOP.EPS
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